wrv32em.git/src/core.rs, branch master a general purpose 32-bit RISC-V emulator https://git.itsnat.dev/wrv32em.git/atom?h=master 2026-07-29T04:25:06Z rework memory system to use actual Sv32 paging 2026-07-29T04:25:06Z Nathan Lee me@nwlee.tech 2026-07-29T04:25:06Z urn:sha1:c43100337514f98c0eeb202980b42b558d303b3e fix memory issues and add basic device discovery 2026-06-17T18:03:33Z Nathan Lee me@nwlee.tech 2026-06-17T18:03:33Z urn:sha1:039afedbc80eea82266c324b6548d59dcd746098 discuss: pci/dtb device discovery? now that the x0 issue is fixed it is entirely possible. implement CSR ops 2026-06-13T02:26:58Z Nathan Lee me@nwlee.tech 2026-06-13T02:26:58Z urn:sha1:5ebbd6d53b6b4a21178e07fdaaeeeee40941c561 fix memory reservation system 2026-06-13T01:47:32Z Nathan Lee me@nwlee.tech 2026-06-13T01:47:32Z urn:sha1:f0007668e61816594734612e7592cbeac1ca5a94 move atomics into core.rs 2026-06-11T03:27:19Z Nathan Lee me@nwlee.tech 2026-06-11T03:27:19Z urn:sha1:f94c087120bf2a241dda51d6311c565dd03b96be move memory and cpu state into its own files 2026-06-11T03:10:59Z Nathan Lee me@nwlee.tech 2026-06-11T03:10:59Z urn:sha1:a37a07533fa9b8bd8962ca3c1aea082ae2548651 add F extension 2026-06-07T01:52:23Z Nathan Lee me@nwlee.tech 2026-06-07T01:52:23Z urn:sha1:615e98a616c851fb6230184029aa4297417cdf6e refactor most extensions in to their own separate core.rs file 2026-06-06T19:29:39Z Nathan Lee me@nwlee.tech 2026-06-06T19:29:39Z urn:sha1:8f39a6cb1568f39c623cdb3e60c2848f3252b196