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<title>wrv32em.git/src/state.rs, branch master</title>
<subtitle>a general purpose 32-bit RISC-V emulator
</subtitle>
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<updated>2026-07-29T04:25:06Z</updated>
<entry>
<title>rework memory system to use actual Sv32 paging</title>
<updated>2026-07-29T04:25:06Z</updated>
<author>
<name>Nathan Lee</name>
<email>me@nwlee.tech</email>
</author>
<published>2026-07-29T04:25:06Z</published>
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</content>
</entry>
<entry>
<title>implement CSR ops</title>
<updated>2026-06-13T02:26:58Z</updated>
<author>
<name>Nathan Lee</name>
<email>me@nwlee.tech</email>
</author>
<published>2026-06-13T02:26:58Z</published>
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<entry>
<title>fix memory reservation system</title>
<updated>2026-06-13T01:47:32Z</updated>
<author>
<name>Nathan Lee</name>
<email>me@nwlee.tech</email>
</author>
<published>2026-06-13T01:47:32Z</published>
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<entry>
<title>chore: lint</title>
<updated>2026-06-11T03:27:34Z</updated>
<author>
<name>Nathan Lee</name>
<email>me@nwlee.tech</email>
</author>
<published>2026-06-11T03:27:34Z</published>
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<id>urn:sha1:0f4993d181bb4dd09a8f2613dd82f267b355fe7e</id>
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<entry>
<title>move atomics into core.rs</title>
<updated>2026-06-11T03:27:19Z</updated>
<author>
<name>Nathan Lee</name>
<email>me@nwlee.tech</email>
</author>
<published>2026-06-11T03:27:19Z</published>
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<id>urn:sha1:f94c087120bf2a241dda51d6311c565dd03b96be</id>
<content type='text'>
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<entry>
<title>move memory and cpu state into its own files</title>
<updated>2026-06-11T03:10:59Z</updated>
<author>
<name>Nathan Lee</name>
<email>me@nwlee.tech</email>
</author>
<published>2026-06-11T03:10:59Z</published>
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