website-kernel/arch/linker.ld


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OUTPUT_ARCH(riscv)
ENTRY(_start)

MEMORY
{
    ROM (rx) : ORIGIN = 0x80000000, LENGTH = 1M
    RAM (rwx) : ORIGIN = 0x80100000, LENGTH = 1M
}

SECTIONS
{
    .text : {
        KEEP(*(.text._start))
        KEEP(*(.text.start))
        *(.text)
        *(.text.*)
    } > ROM
    .rodata : {
        *(.rodata)
        *(.rodata.*)
    } > ROM

    .init_array : {
        __init_array_start = .;
        KEEP(*(.init_array))
        KEEP(*(.init_array.*))
        __init_array_end = .;
    } > ROM

    .data : {
        __data_start = .;
        *(.data)
        *(.data.*)
        __data_end = .;
    } > RAM AT> ROM
    __data_load = LOADADDR(.data);

    .bss : {
        __bss_start = .;
        *(.bss)
        *(.bss.*)
        *(COMMON)
        __bss_end = .;
    } > RAM

    .stack (NOLOAD) : {
        . = ALIGN(16);
        __stack_bottom = .;
        . += 8K;
        __stack_top = .;
    } > RAM
}