implement CSR ops

1 files changed, 30 insertions, 0 deletions

diff --git a/src/core.rs b/src/core.rs
index 9e8e8dd..60d720b 100644
--- a/src/core.rs
+++ b/src/core.rs
@@ -520,3 +520,33 @@ pub fn fclass_s(state: &mut CpuState, rd: usize, rs1: usize) {
         }
     }
 }
+
+pub fn csrrw(state: &mut CpuState, rd: usize, rs1: usize, csr: usize) {
+    state.registers[rd] = state.csr[csr];
+    state.csr[csr] = state.registers[rs1];
+}
+
+pub fn csrrwi(state: &mut CpuState, rd: usize, imm: u32, csr: usize) {
+    state.registers[rd] = state.csr[csr];
+    state.csr[csr] = imm;
+}
+
+pub fn csrrc(state: &mut CpuState, rd: usize, rs1: usize, csr: usize) {
+    state.registers[rd] = state.csr[csr];
+    state.csr[csr] &= !state.registers[rs1];
+}
+
+pub fn csrrci(state: &mut CpuState, rd: usize, imm: u32, csr: usize) {
+    state.registers[rd] = state.csr[csr];
+    state.csr[csr] &= !imm;
+}
+
+pub fn csrrs(state: &mut CpuState, rd: usize, rs1: usize, csr: usize) {
+    state.registers[rd] = state.csr[csr];
+    state.csr[csr] |= state.registers[rs1];
+}
+
+pub fn csrrsi(state: &mut CpuState, rd: usize, imm: u32, csr: usize) {
+    state.registers[rd] = state.csr[csr];
+    state.csr[csr] |= imm;
+}
\ No newline at end of file