diff options
| author | Nathan Lee <me@nwlee.tech> | 2026-06-12 20:47:32 -0500 |
|---|---|---|
| committer | Nathan Lee <me@nwlee.tech> | 2026-06-12 20:47:32 -0500 |
| commit | f0007668e61816594734612e7592cbeac1ca5a94 (patch) | |
| tree | fb17d39b30e1f29da100f8d6fd0dd927fab7b7ad /src/main.rs | |
| parent | 7e2032ec239b78cbda1bef5667ed96d13ebc5bf9 (diff) | |
fix memory reservation system
Diffstat (limited to 'src/main.rs')
| -rw-r--r-- | src/main.rs | 20 |
1 files changed, 7 insertions, 13 deletions
diff --git a/src/main.rs b/src/main.rs index a3571c7..3d8008d 100644 --- a/src/main.rs +++ b/src/main.rs @@ -19,7 +19,10 @@ fn main() { let mut state = CpuState::new(memory); - state.memory.write_multiple_bytes(RO_TARGET as usize, f_dat.as_slice(), 99).unwrap(); + state + .memory + .write_multiple_bytes(RO_TARGET as usize, f_dat.as_slice(), 99) + .unwrap(); state.memory.write(UART_ADDR as usize, 99, 0).unwrap(); state.pc = RO_TARGET; @@ -134,18 +137,9 @@ fn handle_instruction(state: &mut CpuState) { let addr = (state.registers[rs1] + imm) as usize; match f3 { - 0 => { - sb(state, rs1, rs2, imm); - state.release_reservations(&[addr]); - } - 1 => { - sh(state, rs1, rs2, imm); - state.release_reservations(&[addr, addr + 1]); - } - 2 => { - sw(state, rs1, rs2, imm); - state.release_reservations(&[addr, addr + 1, addr + 2, addr + 3]); - } + 0 => sb(state, rs1, rs2, imm), + 1 => sh(state, rs1, rs2, imm), + 2 => sw(state, rs1, rs2, imm), _ => panic!("Illegal instruction: {:x}", word), }; } |
