diff options
| -rw-r--r-- | src/main.rs | 70 |
1 files changed, 40 insertions, 30 deletions
diff --git a/src/main.rs b/src/main.rs index 0ad8162..502d285 100644 --- a/src/main.rs +++ b/src/main.rs @@ -6,9 +6,8 @@ use std::process::exit; use std::sync::{LazyLock, Mutex}; const MEMORY_SIZE: usize = 64 * 1024 * 1024; -static MEMORY: LazyLock<Mutex<Box<[u8]>>> = LazyLock::new(|| { - Mutex::new(vec![0u8; MEMORY_SIZE].into_boxed_slice()) -}); +static MEMORY: LazyLock<Mutex<Box<[u8]>>> = + LazyLock::new(|| Mutex::new(vec![0u8; MEMORY_SIZE].into_boxed_slice())); fn main() { let path = std::path::PathBuf::from("hi"); @@ -74,12 +73,14 @@ fn handle_instruction(memory: &mut Box<[u8]>, registers: &mut [u32], pc: &mut u3 match (f7 << 3) | f3 { 0 => registers[rd] = registers[rs1].wrapping_add(registers[rs2]), // add 256 => registers[rd] = registers[rs1].wrapping_sub(registers[rs2]), // sub - 4 => registers[rd] = registers[rs1] ^ registers[rs2], // xor - 6 => registers[rd] = registers[rs1] | registers[rs2], // or - 7 => registers[rd] = registers[rs1] & registers[rs2], // and + 4 => registers[rd] = registers[rs1] ^ registers[rs2], // xor + 6 => registers[rd] = registers[rs1] | registers[rs2], // or + 7 => registers[rd] = registers[rs1] & registers[rs2], // and 1 => registers[rd] = registers[rs1] << (registers[rs2] & 0b11111), // sll 5 => registers[rd] = registers[rs1] >> (registers[rs2] & 0b11111), // srl - 261 => registers[rd] = ((registers[rs1] as i32) >> (registers[rs2] & 0b11111)) as u32, // sra + 261 => { + registers[rd] = ((registers[rs1] as i32) >> (registers[rs2] & 0b11111)) as u32 + } // sra 2 => { let rs1_signed: i32 = registers[rs1] as i32; let rs2_signed: i32 = registers[rs2] as i32; @@ -93,13 +94,19 @@ fn handle_instruction(memory: &mut Box<[u8]>, registers: &mut [u32], pc: &mut u3 } } // sltu 8 => registers[rd] = registers[rs1].wrapping_mul(registers[rs2]), // mul - 9 => registers[rd] = (((registers[rs1] as i32 as i64) * (registers[rs2] as i32 as i64)) >> 32) as u32, // mulh + 9 => { + registers[rd] = (((registers[rs1] as i32 as i64) + * (registers[rs2] as i32 as i64)) + >> 32) as u32 + } // mulh 10 => { let rs1_signed = (registers[rs1] as i32) as i64; let rs2_unsigned = registers[rs2] as i64; registers[rd] = ((rs1_signed * rs2_unsigned) >> 32) as u32; } // mulhsu - 11 => registers[rd] = ((registers[rs1] as u64 * registers[rs2] as u64) >> 32) as u32, // mulhu + 11 => { + registers[rd] = ((registers[rs1] as u64 * registers[rs2] as u64) >> 32) as u32 + } // mulhu 12 => { let a = registers[rs1] as i32; let b = registers[rs2] as i32; @@ -110,12 +117,14 @@ fn handle_instruction(memory: &mut Box<[u8]>, registers: &mut [u32], pc: &mut u3 } else { (a / b) as u32 }; - }, // div - 13 => registers[rd] = if registers[rs2] == 0 { - u32::MAX - } else { - registers[rs1] / registers[rs2] - }, // divu + } // div + 13 => { + registers[rd] = if registers[rs2] == 0 { + u32::MAX + } else { + registers[rs1] / registers[rs2] + } + } // divu 14 => { let a = registers[rs1] as i32; let b = registers[rs2] as i32; @@ -126,12 +135,14 @@ fn handle_instruction(memory: &mut Box<[u8]>, registers: &mut [u32], pc: &mut u3 } else { (a % b) as u32 } - }, // rem - 15 => registers[rd] = if registers[rs2] == 0 { - registers[rs1] - } else { - registers[rs1] % registers[rs2] - }, //remu + } // rem + 15 => { + registers[rd] = if registers[rs2] == 0 { + registers[rs1] + } else { + registers[rs1] % registers[rs2] + } + } //remu _ => panic!("Illegal instruction: {:x}", word), } @@ -145,9 +156,9 @@ fn handle_instruction(memory: &mut Box<[u8]>, registers: &mut [u32], pc: &mut u3 match f3 { 0 => registers[rd] = registers[rs1].wrapping_add(imm), // addi - 4 => registers[rd] = registers[rs1] ^ imm, // xori - 6 => registers[rd] = registers[rs1] | imm, // ori - 7 => registers[rd] = registers[rs1] & imm, // andi + 4 => registers[rd] = registers[rs1] ^ imm, // xori + 6 => registers[rd] = registers[rs1] | imm, // ori + 7 => registers[rd] = registers[rs1] & imm, // andi 1 => { if (imm >> 5) != 0 { panic!("Illegal instruction: {:x}", word); @@ -161,7 +172,7 @@ fn handle_instruction(memory: &mut Box<[u8]>, registers: &mut [u32], pc: &mut u3 if (imm >> 5) & 0b1111111 == 0 { registers[rd] = registers[rs1] >> (imm & 0b11111); // srli } else { - registers[rd] = ((registers[rs1] as i32 >> (imm & 0b11111))) as u32; // srai + registers[rd] = (registers[rs1] as i32 >> (imm & 0b11111)) as u32; // srai } } 2 => { @@ -236,11 +247,10 @@ fn handle_instruction(memory: &mut Box<[u8]>, registers: &mut [u32], pc: &mut u3 let rs1 = ((word >> 15) & 0b11111) as usize; let rs2 = ((word >> 20) & 0b11111) as usize; - let imm = - (((word >> 31) & 0x1) << 12) - | (((word >> 7) & 0x1) << 11) - | (((word >> 25) & 0x3f) << 5) - | (((word >> 8) & 0xf) << 1); + let imm = (((word >> 31) & 0x1) << 12) + | (((word >> 7) & 0x1) << 11) + | (((word >> 25) & 0x3f) << 5) + | (((word >> 8) & 0xf) << 1); let imm = ((imm as i32) << 19 >> 19) as u32; |