1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
|
use crate::state::CpuState;
use std::num::FpCategory;
pub fn add(state: &mut CpuState, rd: usize, rs1: usize, rs2: usize) {
state.registers[rd] = state.registers[rs1].wrapping_add(state.registers[rs2]);
}
pub fn sub(state: &mut CpuState, rd: usize, rs1: usize, rs2: usize) {
state.registers[rd] = state.registers[rs1].wrapping_sub(state.registers[rs2]);
}
pub fn xor(state: &mut CpuState, rd: usize, rs1: usize, rs2: usize) {
state.registers[rd] = state.registers[rs1] ^ state.registers[rs2];
}
pub fn or(state: &mut CpuState, rd: usize, rs1: usize, rs2: usize) {
state.registers[rd] = state.registers[rs1] | state.registers[rs2];
}
pub fn and(state: &mut CpuState, rd: usize, rs1: usize, rs2: usize) {
state.registers[rd] = state.registers[rs1] & state.registers[rs2];
}
pub fn sll(state: &mut CpuState, rd: usize, rs1: usize, rs2: usize) {
state.registers[rd] = state.registers[rs1] << (state.registers[rs2] & 0b11111);
}
pub fn srl(state: &mut CpuState, rd: usize, rs1: usize, rs2: usize) {
state.registers[rd] = state.registers[rs1] >> (state.registers[rs2] & 0b11111);
}
pub fn sra(state: &mut CpuState, rd: usize, rs1: usize, rs2: usize) {
state.registers[rd] =
((state.registers[rs1] as i32) >> (state.registers[rs2] & 0b11111)) as u32;
}
pub fn slt(state: &mut CpuState, rd: usize, rs1: usize, rs2: usize) {
let rs1_signed = state.registers[rs1] as i32;
let rs2_signed = state.registers[rs2] as i32;
state.registers[rd] = if rs1_signed < rs2_signed { 1 } else { 0 };
}
pub fn sltu(state: &mut CpuState, rd: usize, rs1: usize, rs2: usize) {
state.registers[rd] = if state.registers[rs1] < state.registers[rs2] {
1
} else {
0
};
}
pub fn mul(state: &mut CpuState, rd: usize, rs1: usize, rs2: usize) {
state.registers[rd] = state.registers[rs1].wrapping_mul(state.registers[rs2]);
}
pub fn mulh(state: &mut CpuState, rd: usize, rs1: usize, rs2: usize) {
state.registers[rd] = (((state.registers[rs1] as i32 as i64)
* (state.registers[rs2] as i32 as i64))
>> 32) as u32;
}
pub fn mulhsu(state: &mut CpuState, rd: usize, rs1: usize, rs2: usize) {
let rs1_signed = (state.registers[rs1] as i32) as i64;
let rs2_unsigned = state.registers[rs2] as i64;
state.registers[rd] = ((rs1_signed * rs2_unsigned) >> 32) as u32;
}
pub fn mulhu(state: &mut CpuState, rd: usize, rs1: usize, rs2: usize) {
state.registers[rd] =
((state.registers[rs1] as u64 * state.registers[rs2] as u64) >> 32) as u32;
}
pub fn div(state: &mut CpuState, rd: usize, rs1: usize, rs2: usize) {
let a = state.registers[rs1] as i32;
let b = state.registers[rs2] as i32;
state.registers[rd] = if b == 0 {
u32::MAX
} else if a == i32::MIN && b == -1 {
a as u32
} else {
(a / b) as u32
};
}
pub fn divu(state: &mut CpuState, rd: usize, rs1: usize, rs2: usize) {
state.registers[rd] = if state.registers[rs2] == 0 {
u32::MAX
} else {
state.registers[rs1] / state.registers[rs2]
};
}
pub fn rem(state: &mut CpuState, rd: usize, rs1: usize, rs2: usize) {
let a = state.registers[rs1] as i32;
let b = state.registers[rs2] as i32;
state.registers[rd] = if b == 0 {
a as u32
} else if a == i32::MIN && b == -1 {
0
} else {
(a % b) as u32
};
}
pub fn remu(state: &mut CpuState, rd: usize, rs1: usize, rs2: usize) {
state.registers[rd] = if state.registers[rs2] == 0 {
state.registers[rs1]
} else {
state.registers[rs1] % state.registers[rs2]
};
}
pub fn addi(state: &mut CpuState, rd: usize, rs1: usize, imm: u32) {
state.registers[rd] = state.registers[rs1].wrapping_add(imm);
}
pub fn xori(state: &mut CpuState, rd: usize, rs1: usize, imm: u32) {
state.registers[rd] = state.registers[rs1] ^ imm;
}
pub fn ori(state: &mut CpuState, rd: usize, rs1: usize, imm: u32) {
state.registers[rd] = state.registers[rs1] | imm;
}
pub fn andi(state: &mut CpuState, rd: usize, rs1: usize, imm: u32) {
state.registers[rd] = state.registers[rs1] & imm;
}
pub fn slli(state: &mut CpuState, rd: usize, rs1: usize, imm: u32) {
state.registers[rd] = state.registers[rs1] << (imm & 0b11111);
}
pub fn srli(state: &mut CpuState, rd: usize, rs1: usize, imm: u32) {
state.registers[rd] = state.registers[rs1] >> (imm & 0b11111);
}
pub fn srai(state: &mut CpuState, rd: usize, rs1: usize, imm: u32) {
state.registers[rd] = ((state.registers[rs1] as i32) >> (imm & 0b11111)) as u32;
}
pub fn slti(state: &mut CpuState, rd: usize, rs1: usize, imm: u32) {
state.registers[rd] = if (state.registers[rs1] as i32) < (imm as i32) {
1
} else {
0
};
}
pub fn sltiu(state: &mut CpuState, rd: usize, rs1: usize, imm: u32) {
state.registers[rd] = if state.registers[rs1] < imm { 1 } else { 0 };
}
pub fn lb(state: &mut CpuState, rd: usize, rs1: usize, imm: u32) {
let byte = state
.memory
.read((state.registers[rs1] + imm) as usize, 99)
.unwrap();
state.registers[rd] = (byte as i8) as u32;
}
pub fn lh(state: &mut CpuState, rd: usize, rs1: usize, imm: u32) {
let bytes = state
.memory
.read_multiple_bytes((state.registers[rs1] + imm) as usize, 2, 99)
.unwrap();
state.registers[rd] = (((bytes[1] as u16) << 8 | bytes[0] as u16) as i16) as u32;
}
pub fn lw(state: &mut CpuState, rd: usize, rs1: usize, imm: u32) {
let addr = (state.registers[rs1] + imm) as usize;
let slice = state.memory.read_multiple_bytes(addr, 4, 99).unwrap();
let number = u32::from_le_bytes(slice[0..4].try_into().unwrap());
state.registers[rd] = number;
}
pub fn lbu(state: &mut CpuState, rd: usize, rs1: usize, imm: u32) {
state.registers[rd] = state
.memory
.read((state.registers[rs1] + imm) as usize, 99)
.unwrap() as u32;
}
pub fn lhu(state: &mut CpuState, rd: usize, rs1: usize, imm: u32) {
let bytes = state
.memory
.read_multiple_bytes((state.registers[rs1] + imm) as usize, 2, 99)
.unwrap();
state.registers[rd] = ((bytes[1] as u16) << 8 | bytes[0] as u16) as u32;
}
pub fn sb(state: &mut CpuState, rs1: usize, rs2: usize, imm: u32) {
state
.memory
.write(
(state.registers[rs1] + imm) as usize,
99,
state.registers[rs2] as u8,
)
.unwrap();
}
pub fn sh(state: &mut CpuState, rs1: usize, rs2: usize, imm: u32) {
let halfword = state.registers[rs2] & 0xFFFF;
let index = (state.registers[rs1] + imm) as usize;
state
.memory
.write_multiple_bytes(index, &[(halfword & 0xFF) as u8, (halfword >> 8) as u8], 99)
.unwrap();
}
pub fn sw(state: &mut CpuState, rs1: usize, rs2: usize, imm: u32) {
let index = (state.registers[rs1] + imm) as usize;
state
.memory
.write_multiple_bytes(index, &state.registers[rs2].to_le_bytes(), 99)
.unwrap();
}
pub fn beq(state: &mut CpuState, rs1: usize, rs2: usize, imm: u32) {
if state.registers[rs1] == state.registers[rs2] {
state.pc += imm;
}
}
pub fn bne(state: &mut CpuState, rs1: usize, rs2: usize, imm: u32) {
if state.registers[rs1] != state.registers[rs2] {
state.pc += imm;
}
}
pub fn blt(state: &mut CpuState, rs1: usize, rs2: usize, imm: u32) {
if (state.registers[rs1] as i32) < (state.registers[rs2] as i32) {
state.pc += imm;
}
}
pub fn bge(state: &mut CpuState, rs1: usize, rs2: usize, imm: u32) {
if (state.registers[rs1] as i32) >= (state.registers[rs2] as i32) {
state.pc += imm;
}
}
pub fn bltu(state: &mut CpuState, rs1: usize, rs2: usize, imm: u32) {
if state.registers[rs1] < state.registers[rs2] {
state.pc += imm;
}
}
pub fn bgeu(state: &mut CpuState, rs1: usize, rs2: usize, imm: u32) {
if state.registers[rs1] >= state.registers[rs2] {
state.pc += imm;
}
}
pub fn jal(state: &mut CpuState, rd: usize, imm: u32) {
state.registers[rd] = state.pc + 4;
state.pc += imm;
}
pub fn jalr(state: &mut CpuState, rd: usize, rs1: usize, imm: u32) {
state.registers[rd] = state.pc + 4;
state.pc = state.registers[rs1] + imm;
}
pub fn lui(state: &mut CpuState, rd: usize, imm: u32) {
state.registers[rd] = imm << 12;
}
pub fn auipc(state: &mut CpuState, pc: u32, rd: usize, imm: u32) {
state.registers[rd] = pc + (imm << 12);
}
pub fn fmadd_s(state: &mut CpuState, rd: usize, rs1: usize, rs2: usize, rs3: usize) {
state.f_registers[rd] =
state.f_registers[rs1] * state.f_registers[rs2] + state.f_registers[rs3];
}
pub fn fmsub_s(state: &mut CpuState, rd: usize, rs1: usize, rs2: usize, rs3: usize) {
state.f_registers[rd] =
state.f_registers[rs1] * state.f_registers[rs2] - state.f_registers[rs3];
}
pub fn fnmadd_s(state: &mut CpuState, rd: usize, rs1: usize, rs2: usize, rs3: usize) {
state.f_registers[rd] =
-state.f_registers[rs1] * state.f_registers[rs2] + state.f_registers[rs3];
}
pub fn fnmsub_s(state: &mut CpuState, rd: usize, rs1: usize, rs2: usize, rs3: usize) {
state.f_registers[rd] =
-state.f_registers[rs1] * state.f_registers[rs2] - state.f_registers[rs3];
}
pub fn fadd_s(state: &mut CpuState, rd: usize, rs1: usize, rs2: usize) {
state.f_registers[rd] = state.f_registers[rs1] + state.f_registers[rs2];
}
pub fn fsub_s(state: &mut CpuState, rd: usize, rs1: usize, rs2: usize) {
state.f_registers[rd] = state.f_registers[rs1] - state.f_registers[rs2];
}
pub fn fmul_s(state: &mut CpuState, rd: usize, rs1: usize, rs2: usize) {
state.f_registers[rd] = state.f_registers[rs1] * state.f_registers[rs2];
}
pub fn fdiv_s(state: &mut CpuState, rd: usize, rs1: usize, rs2: usize) {
let a = state.f_registers[rs1];
let b = state.f_registers[rs2];
state.f_registers[rd] = if b == 0.0 {
f32::NAN
// todo: raise division by zero in csr
} else {
a / b
}
}
pub fn fsqrt_s(state: &mut CpuState, rd: usize, rs1: usize) {
state.f_registers[rd] = state.f_registers[rs1].sqrt();
}
pub fn fsgnj_s(state: &mut CpuState, rd: usize, rs1: usize, rs2: usize) {
state.f_registers[rd] = state.f_registers[rs1].abs() * state.f_registers[rs2].signum();
}
pub fn fsgnjn_s(state: &mut CpuState, rd: usize, rs1: usize, rs2: usize) {
state.f_registers[rd] = state.f_registers[rs1].abs() * -state.f_registers[rs2].signum();
}
pub fn fsgnjx_s(state: &mut CpuState, rd: usize, rs1: usize, rs2: usize) {
state.f_registers[rd] = state.f_registers[rs1] * state.f_registers[rs2].signum();
}
pub fn fmin_s(state: &mut CpuState, rd: usize, rs1: usize, rs2: usize) {
state.f_registers[rd] = state.f_registers[rs1].min(state.f_registers[rs2]);
}
pub fn fmax_s(state: &mut CpuState, rd: usize, rs1: usize, rs2: usize) {
state.f_registers[rd] = state.f_registers[rs1].max(state.f_registers[rs2]);
}
pub fn fcvt_s_w(state: &mut CpuState, rd: usize, rs1: usize) {
state.f_registers[rd] = state.registers[rs1] as i32 as f32;
}
pub fn fcvt_s_wu(state: &mut CpuState, rd: usize, rs1: usize) {
state.f_registers[rd] = state.registers[rs1] as f32;
}
pub fn fcvt_w_s(state: &mut CpuState, rd: usize, rs1: usize) {
state.registers[rd] = state.f_registers[rs1] as i32 as u32;
}
pub fn fcvt_wu_s(state: &mut CpuState, rd: usize, rs1: usize) {
state.registers[rd] = state.f_registers[rs1] as u32;
}
pub fn fmv_x_w(state: &mut CpuState, rd: usize, rs1: usize) {
state.registers[rd] = u32::from_le_bytes(state.f_registers[rs1].to_le_bytes());
}
pub fn fmv_w_x(state: &mut CpuState, rd: usize, rs1: usize) {
state.f_registers[rd] = f32::from_le_bytes(state.registers[rs1].to_le_bytes());
}
pub fn feq_s(state: &mut CpuState, rd: usize, rs1: usize, rs2: usize) {
state.registers[rd] = if state.f_registers[rs1] == state.f_registers[rs2] {
1
} else {
0
}
}
pub fn flt_s(state: &mut CpuState, rd: usize, rs1: usize, rs2: usize) {
state.registers[rd] = if state.f_registers[rs1] < state.f_registers[rs2] {
1
} else {
0
}
}
pub fn fle_s(state: &mut CpuState, rd: usize, rs1: usize, rs2: usize) {
state.registers[rd] = if state.f_registers[rs1] <= state.f_registers[rs2] {
1
} else {
0
}
}
pub fn fclass_s(state: &mut CpuState, rd: usize, rs1: usize) {
let number = state.f_registers[rs1];
let class = number.classify();
let frac_msb = (number.to_bits() >> 22) & 0x01;
state.registers[rd] = match class {
FpCategory::Nan => {
if frac_msb == 0 {
0b1
} else {
0b10
}
}
FpCategory::Infinite => {
if number.is_sign_negative() {
0b100
} else {
0b100000000
}
}
FpCategory::Zero => {
if number.is_sign_negative() {
0b10000
} else {
0b100000
}
}
FpCategory::Subnormal => {
if number.is_sign_negative() {
0b1000
} else {
0b1000000
}
}
FpCategory::Normal => {
if number.is_sign_negative() {
0b100
} else {
0b10000000
}
}
}
}
|
